RISC-V Technical Session | Hardware-Based Detection of Stack Buffer Overflow Attacks on RISC-V

This Tech Session evaluates the effectiveness of hardware-based approaches in detecting stack buffer overflow (SBO) attacks on RISC-V systems. Presenters conducted simulations on the PULP platform, examining micro-architecture events using semi-supervised anomaly detection techniques. The findings highlighted challenges in detection performance, suggesting that a combined approach using both software and hardware detectors might be more effective, with hardware serving as the primary defense. These hardware-based approaches offer significant benefits that could enhance RISC-V-based architectures. This work was supported by Project SERICS through the MUR National Recovery and Resilience Plan, funded by the European Union—NextGenerationEU under Grant PE00000014, and by the Vitamin-V Project, funded by the European Union under Project 101093062. Presenters: Alessandro Savino, Associate Professor - Politecnico di Torino Cristiano Chenet, Ph.D. Candidate - Politecnico di Torino Stefano Di Carlo, Full Professor - Politecnico di Torino