FPGA 23 - DSP FIR Lowpass Filter with Verilog

In this episode, we’re building a 9-tap finite impulse response (FIR) lowpass filter in Verilog that has a cutoff frequency at ~10MHz with a 100MHz sampling clock. In order to test this FIR lowpass filter, we’re also building a testbench that synthesize two sine waves, one at 2MHz and the other at 30MHz. These two sine waves are added together and the resulting noisy signal is resampled at 100MHz before feeding the FIR lowpass filter. As you will see, the FIR lowpass filter would attenuate the 30MHz component of the noisy signal and leave the 2MHz component untouched. #fpga #vivado #verilog #xilinx #dsp #impulseresponse #simulation Recommended prerequisite: FPGA 18 - Xilinx Verilog Cordic Sine/Cosine generator FPGA 7 - Verilog Vivado two’s complement fixed-point arithmetic