Vitruvius: An Area-Efficient RISC-V Decoupled Vector Ac... Francesco Minervini & Oscar Palomar Perez

Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing - Francesco Minervini & Oscar Palomar Perez, Barcelona Supercomputing Center - BSC The availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores. This talk presents Vitruvius, the first RISC-V vector accelerator developed at BSC for the Supercomputing domain. Vitruvius is compliant with the RISC-V vector extension specification . and can be easily connected to a scalar core using the Open Vector Interface (OVI) standard in a plug-and-play fashion. Vitruvius natively supports long vectors: 256 Double Precision (DP) floating-point elements in a single vector instruction. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File (VRF) and functional units (one integer, one floating-point). It adopts a novel hybrid in-order/out-o