Efficient Issue Scheduling for Hardware Multithreaded RISC-V... Dr. Shlomo Greenberg & Sami Shamoon

Efficient Issue Scheduling for Hardware Multithreaded RISC-V Pipeline - Dr. Shlomo Greenberg, Ben Gurion University of the Negev & Sami Shamoon College Engineering, Beer-Sheva, Israel Hardware multithreading is a common approach for tolerating memory latency by utilizing idle cycles and avoid- ing CPU stalling. Nowadays, multithreading architectures are commonly used across many processors and various embedded edge devices to improve performance. This work suggests a new multithreading in-order pipeline microarchitecture design for RISC-V and proposes an efficient event-based issue scheduling algorithm. The proposed scheduling algorithm is based on the unique RISC-V ISA that enables decoding of the instruction type in an early stage of the pipeline. The RISC-V-based mul- tithreading architecture is evaluated using a dedicated software simulator. Simulation results show that the proposed algorithm outperforms the classical Round Robin and the coarse grain algorithms. The proposed architecture is evaluated usi