DAC 2019 Demo - Partitioning Design for Multi FPGA Prototyping

Multi-FPGA partitioning has always been a challenge due to limited number of FPGA I/Os and FPGA-specific clocking tree. Aldec provides HES-DVM Prototyping toolbox that automates design partitioning for multiple FPGAs and integrates ultra-fast HES Proto-AXI host bridge. This year we will demonstrate the new features and improvements that include: Automatic Partitions, Connections, Routing and third-party FPGA boards support.