How to pass return loss compliance metric for 32 GT/s PCIE 5.0?

Have you ever faced a return loss compliance test failure for a PCB link? Like I did in my previous post for 32 GT/s PCIE 5.0 standard How to fix it? First of all, adjust the trace width to match the target characteristic impedance more closely. This was shown in an earlier post Next, reduced the reflection from discontinuities such as AC capacitor, BGA and connector pads. This was done with simple cut-outs in reference plane in Simbeor software, as you can see in the video below. (Better resolution is at ). This made the link pass the return loss test! However, there is still room for improvement. The microstrip traces (reddish in the ERC) and the viaholes (red in the ERC) have impedance substantially higher than 100 Ohm on TDR, which causes the reflections. I will show you how I solved this problem with Simbeor software in my next post. Stay tuned for more tips and tricks on PCB design and simulation! #simbeor #electromagnetics #signal_integrity