1.2 - Racing Down the Slopes of Moore’s Law (Bram Nauta)

Bram Nauta, University of Twente, Enschede, The Netherlands. Since its inception, Moore’s Law has been the driving force for IC design. Although during the first decade, “everything” seemed to be better, however, we lost the scaling of processor clock speed and RF transistor speed, and now it looks as if power efficiency of digital gates will stall. What remains is scaling in transistor count and cost-per-function, thanks to 3D integration. Thus, this is an excellent moment to reconsider how we design for analog and digital signal processing. The higher the required signal-to-noise ratio (SNR), the more power-efficient digital signal processing is compared to analog. Pure analog processing remains more efficient only for ~30dB SNR or less. In the case of digital processing, the conversion from analog to digital should therefore be made as early in the signal chain as possible. Thanks to the figure-of-merit race, analogto-digital converters (ADCs) have experienced a tremendous win in power efficiency. However, these ADCs require a large input voltage swing while the input signals to be converted, from an antenna or sensor interface, are usually much smaller. Therefore, RF and analog front-ends are needed, which consume much more power than the ADCs to be driven. Let us re-think these analog front-ends. Can we still efficiently design these frontends in future CMOS? Do we need so much linear amplification? Do we need active linear circuits at all? Can we not use “digital” components to replace the analog front-ends and ADCs?