Modeling and Simulating a Power-Aware Parallel Bus System: Part 1

For an accurate analysis of DDR4, it is very important to incorporate the Power Delivery Network into the simulation and analyze the effect of noise due to switching of the parallel bus signal groups. In this series of videos, we’ll learn how to model, simulate, and analyze a Power-Aware Parallel Bus System. Part 1 of 5 will teach you how to create a power-aware parallel bus system topology and analyze return loss results. Follow along with these demo files: [00:00] Introduction [00:24] Open the Topology [01:24] Modify the Existing Topology [03:16] View S-Parameter Plots [04:58] Save the Topology Do you have any questions, tips, or ideas about DDR Simulation and Analysis? Let us know in the comments section below! ________________________________________ Take the Sigrity Challenge- #Sigrity-Challenge __________________________________________ About Us: EMA Design Automation is a leader in product development solutions ranging from electrical CAD tools, data management and PLM systems, services, training, and technical support. Learn more about EMA Design Automation at Let’s Connect! Subscribe – Website – Facebook – LinkedIn – Twitter –