KIM-1, MTU Visable Memory, and Memory Tests

I’ve been working on a MTU “Visable Memory“ video board for a customer, which is a bitmapped video board for the KIM-1. Final stages of repair include running an exhaustive memory test against the board, which provides some interesting visuals, since it’s a bitmapped display, and not a character display. During testing, I found that our usual go-to 6502 memory test, the test provided by Ohio Scientific (OSI), apparently has a pathological case with page-aligned faults in which a bit from the previous page can affect a bit in a subsequent page. It’s clear from the visual pattern generated by running the OSI test on the Visable Memory board that there is indeed a distinct page-aligned pattern to it, which is a consequence of how OSI was generating their test pattern. To deal with this, I ended up porting Martin Eberhard’s MTEST4 walking bit test for the Altair 680 to 6502 and KIM-1 I/O. Martin’s test uses a bit pattern designed to trigger sensitivities. The pattern is